| DOUTDIN | Set the bit to enable full duplex communication. 1: enable 0: disable. |
| CS_HOLD | spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable. |
| CS_SETUP | spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable. |
| CK_I_EDGE | In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits. |
| CK_OUT_EDGE | the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. |
| RD_BYTE_ORDER | In read-data (MISO) phase 1: big-endian 0: little_endian |
| WR_BYTE_ORDER | In command address write-data (MOSI) phases 1: big-endian 0: litte_endian |
| FWRITE_DUAL | In the write operations read-data phase apply 2 signals |
| FWRITE_QUAD | In the write operations read-data phase apply 4 signals |
| FWRITE_DIO | In the write operations address phase and read-data phase apply 2 signals. |
| FWRITE_QIO | In the write operations address phase and read-data phase apply 4 signals. |
| SIO | Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. |
| USR_HOLD_POL | It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low |
| USR_DOUT_HOLD | spi is hold at data out state the bit combined with spi_usr_hold_pol bit. |
| USR_DIN_HOLD | spi is hold at data in state the bit combined with spi_usr_hold_pol bit. |
| USR_DUMMY_HOLD | spi is hold at dummy state the bit combined with spi_usr_hold_pol bit. |
| USR_ADDR_HOLD | spi is hold at address state the bit combined with spi_usr_hold_pol bit. |
| USR_CMD_HOLD | spi is hold at command state the bit combined with spi_usr_hold_pol bit. |
| USR_PREP_HOLD | spi is hold at prepare state the bit combined with spi_usr_hold_pol bit. |
| USR_MISO_HIGHPART | read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. |
| USR_MOSI_HIGHPART | write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. |
| USR_DUMMY_IDLE | spi clock is disable in dummy phase when the bit is enable. |
| USR_MOSI | This bit enable the write-data phase of an operation. |
| USR_MISO | This bit enable the read-data phase of an operation. |
| USR_DUMMY | This bit enable the dummy phase of an operation. |
| USR_ADDR | This bit enable the address phase of an operation. |
| USR_COMMAND | This bit enable the command phase of an operation. |